PIC16F505T-I/SL【PDF 37/44 页】IC MCU FLASH 1KX12 14SOIC

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Sheet目录3896

33页 34页 35页 36页 [37页]38页 39页 40页 41页

6062LS–ATARM–23-Mar-09

AT91SAM9261

6062DS

Corrected MIPS and speed on page 1.

2292

Added information on EBI NCS0 hwhen BMS = 0 in Table 8-3, “Internal Memory Mapping,” on page 18.

6062ES

2946

Updated information on JTAGSEL in Section 3-1 “Signal Description by Peripheral” on page 5 and in

Section 6.1 “JTAG Port Pins” on page 11.

2475

Reformatted Section 8. “Memories” on page 16. Inserted new Figure 8-1, “AT91SAM9261 Memory

Mapping,” on page 16 to show full product memory mapping.

2474

Removed information on Timer Counter clock assignments in Section 10.11 “Timer Counter” on page

37.

2480

Inserted new Section 8.1.2 “Boot Strategies” on page 20 to replace Boot ROM section.

6062FS

3068

Changed pin name for ball D9 to SHDN in Table 4-1, “AT91SAM9261 Pinout for 217-ball LFBGA

Package (1),” on page 10.

3147

Updated information on shutdown pin in Section 6.5 “Shutdown Logic Pins” on page 12.

3067

Updated peripheral mnemonics in Figure 8-1, “AT91SAM9261 Memory Mapping,” on page 16.

3503

Added note to Table 10-1, “Peripheral Identifiers,” on page 28.

6062GS

3660, 3695

Updated VDDOSC, VDDPLL and VDDIOM ranges in”Features”, Table 3-1, “Signal Description by

Peripheral,” on page 5 and Section 5.2 “Power Consumption” on page 11.

3660

Added ROM to Figure 8-1, “AT91SAM9261 Memory Mapping,” on page 16.

6062HS

3491

Updated Section 9.6 “Power Management Controller” on page 25 and Figure 9-3, “Power Management

Controller Block Diagram,” on page 25.

Added Section 11. “Package Drawing” on page 39.

6062IS

5042

Table 10-4, “Multiplexing on PIO Controller C,” on page 33,

PCO - PC7 and PC12-PC13 power supplies are VDDIOP not VDDIOM.

Table 10-2, “Multiplexing on PIO Controller A,” on page 31

PA30-PA31 power supplies are VDDIOP not VDDIOM

5027

rfo

Section 8.1.2 “Boot Strategies”, removed sentence pertaining to “remap”

Section 8.1.2.1 “BMS = 1, Boot on Embedded ROM”, added NANDFlash Boot.

4965

Section 5.1 “Power Supplies”, startup voltage slope requirements for VDDCORE and VDDBU added.

4844

Table 10-3, “Multiplexing on PIO Controller B,” on page 32, Note added to “PB3” comments

4835

Figure 9-3, “Power Management Controller Block Diagram,” on page 25, in the master memory

controller representation, the divider has been updated.

4241

Table 4-1 on page 10,

PCO - PC7, PC8 - PC11, PC12 - PC15 power supplies are VDDIOP not VDDIOM.

6062JS

5250

Section 5.2 “Power Consumption”, startup voltage slope requirements for VDDCORE and VDDBU

removed.

5248

In Features, on page 2: Required Power Supply updated, 3.0V to 3.6V for VDDOSC and for VDDPLL

Table 13-1.

Revision History (Continued)

Doc.

Rev.

Source

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